This invention relates to fabrication of a semiconductor integrated circuit device. More particularly, this invention relates to a technology which will be effective when applied to a xe2x80x9cSalicidexe2x80x9d (self-aligned silicide) process using a Co (cobalt) film formed by sputtering.
Polycrystalline silicon and Al (aluminum) have been used mainly in the past as electrode and wiring materials of semiconductor integrated circuits formed on a Si (silicon) substrate. As semiconductor devices have been scaled down in recent years, however, attempts have been made to introduce refractory metals such as W (tungsten), Ti (titanium), cobalt, etc, and their silicide compounds, as new electrode and wiring materials because these metals and metal compounds have a lower resistance than Si and a higher electromigration resistance than Al.
The refractory metal (silicide) film for these electrode and wiring materials is formed on a semiconductor wafer by sputtering, in argon, a target that is prepared by sintering powder formed of a refractory metal (silicide).
Japanese Patent Laid-Open Nos. 192974/1994, 192979/1994 and 3486/1995 disclose a technology for producing high purity Co which reduces its impurity contents, particularly the Ni (nickel) and Fe (iron) contents, and has a purity of over 99.999% (5N), by an electrolytic refining process. This high purity Co is applied to the production of a Co target for forming a Co film used for the electrodes and wiring lines (electrodes, gates, wiring lines, devices, protective films, etc.) of semiconductor devices.
Japanese Patent Laid-Open No. 1370/1993 describes a method of producing a refractory metal silicide target for sputtering, which method is capable of restricting the formation of particles that would otherwise result in breakage and a short-circuit of the electrodes and wiring lines. This publication mentions W, Mo (molybdenum), Ta (tantalum), Ti, Co and Cr (chromium) as the refractory metals.
A refractory metal silicide film can be formed by a refractory metal film to react with silicon, besides the method described above that uses the target of the refractory metal silicide.
Japanese Patent Laid-Open No. 321069/1995 describes a so-called xe2x80x9cSalicide processxe2x80x9d which comprises the steps of forming a Coxe2x80x94Ti film on the entire surface of a semiconductor substrate, on which MOSFETs (Metal Oxide Semiconductor Field Effect transistors) are formed, by a magnetron sputtering process using a composite metal target constituted by 20 atom % of a ferromagnetic material, such as Co, and 80 atom % of a paramagnetic material such as Ti, and then conducting heat-treatment so as to form a Co silicide-Ti silicide mixture layer on the polycrystalline silicon gates as well as on the sources and drains, followed by removing unreacted portions of the mixture layer by etching, and conducting again the heat-treatment to thereby reduce the resistance of the mixture layer.
In order to achieve a high operation speed, high performance and low power consumption of large-scale semiconductor devices using very small MOSFETs fabricated by a deep sub-micron design rule of not greater than 0.25 xcexcm, for example, it is essentially necessary to achieve a high-speed operation of discrete MOSFETs, in addition to a reduction of the delay in wiring lines. In this regard, the source/drain resistance of the MOSFET increases when the MOSFET is scaled down, and this increase in the resistance is a critical factor that impedes the high-speed operation of the transistors. In the case of low power consumption devices for driving the transistors at a low voltage of 2 V or below, in particular, an improvement of a operation speed of the discrete MOSFET is a critical problem.
When the MOSFET is driven at the low voltage of 2 V or below, it becomes difficult to control a threshold voltage (Vth) in a buried channel type structure, in which the gate electrode is constituted by n type polycrystalline silicon, as is the case with p channel MOSFETs of the prior art. Therefore, how to control the threshold voltage is another problem.
The inventors of the present invention have examined the introduction of the Salicide process for forming a low-resistance high melting silicide layer on the polycrystalline silicon gates and on both source and drain so as to solve the problem of the high-speed operation of the MOSFET. The inventors have selected Co (cobalt) that provides a low resistance silicide of about 15 xcexcxcexa9cm as a refractory metal material. To control the threshold voltage of the MOSFET, on the other hand, the inventors have attempted to introduce a dual-gate CMOS structure in which the gate electrode of p channel MOSFETs is constituted into a surface channel type by p type polycrystalline silicon while the gate electrode of n channel MOSFETs is constituted into the surface channel type by n type polycrystalline silicon. To introduce this dual-gate CMOS structure, the connection method of the p type polycrystalline silicon gate and the n type polycrystalline silicon gate becomes the problem, but this problem can be solved by combining this structure with the Salicide process for forming the silicide layer on the polycrystalline silicon gates.
The process for forming the Co silicide layer on the polycrystalline silicon gates and on the source and drain of the MOSFET is as follows.
First, a Co film is deposited on a semiconductor substrate having MOSFETs formed thereon, by a sputtering process using a Co target, and heat-treatment is then effected so as to permit Co and Si to react with each other and to thereby form a Co silicide layer on the surface of each of the gate, source and drain (first heat-treatment). The Co silicide obtained at this time is a mono-silicide (CoSi) having a relatively high resistance of 50 to 60 xcexcxcexa9cm. After the unreacted Co film is removed by wet etching, heat-treatment is carried out once again to cause the phase transition of the mono-silicide to a di-silicide (CoSi2) having a low resistance (second heat-treatment).
When the present inventors have carried out the first heat-treatment for the Co film formed by using a Co target having a purity of 99.9%, however, the film thickness of the resulting Co mono-silicide (CoSi) exhibits high dependence on the temperature change of the heat-treatment. More concretely, a phenomenon is observed in which the film thickness becomes greater with a higher heat-treatment temperature and smaller with a lower heat-treatment temperature. Consequently, the film thickness cannot be controlled stably. Presumably, such a variation of the film thickness results mainly from silicidization of a part of the impurity transition metals, such as Fe and Ni, contained in the Co target.
The result of the studies described above suggests that in order to obtain a Co silicide layer having a low resistance, the film thickness of the mono-silicide layer must be made sufficiently large by setting the temperature of the first heat-treatment to a high level. When the film thickness of the mono-silicide layer becomes large, however, a junction leakage current increases in 0.25 xcexcm MOS devices in which the source-drain p-n junction is shallower than 0.3 xcexcm. It is assumed that excessive inter-lattice Si formed by the reaction between Co, which enters the substrate, and Si, gathers and grows to thereby invite this increase in the junction leakage current.
If the first heat-treatment temperature is raised, an undesirable silicidization reaction is likely to occur at the source-drain end portion and to result in so-called xe2x80x9ccreep-upxe2x80x9d, or a phenomenon occurs in which the silicide layer extends up to the field insulating film and the gate side wall insulating film. As a result, short-circuit develops in MOSFETs of a very small size between the gate and the source, between the gate and the drain and between the sources and the drains of adjacent MOSFETs. When the first heat-treatment is applied to the dual gate CMOSs, in particular, B (boron) as the impurity in p type polycrystalline silicon, that constitutes the gate electrode of the p channel MOSFET, is likely to diffuse into the gate oxide film with the result that the electric characteristics of the transistors are likely to fluctuate.
On the other hand, when the film thickness of the mono-silicide layer is reduced by setting the first heat-treatment temperature to a low level so as to avoid an increase in the junction leakage current, the resistance of the silicide layer increases. When the heat-treatment temperature is low, the progress of the silicidization reaction becomes slow, too, so that the resistance of the silicide layer further increases. Furthermore, the heat resistance of the Co silicide layer drops when its film thickness becomes small. In consequence, agglomeration of the crystal grains of the Co silicide occurs during the heat-treatment process after the formation of the MOSFET (e.g. the process in which a silicon oxide film containing P (phosphorus) doped thereto is deposited on the MOSFET and is then sintered at a high temperature in order to getter a metal such as Na (sodium)). Consequently, an abnormal increase in the resistance occurs.
Therefore, a method of fabricating a semiconductor integrated circuit device according to the present invention comprises the following steps (a) to (d):
(a) a step of forming MOSFETs on a main plane of a wafer;
(b) a step of depositing a Co film to regions of the main plane of the wafer including at least the upper portions of the gate electrode and the source and drain of the MOSFET by sputtering using a high purity Co target;
(c) a step of forming a Co silicide layer on the surface of the gate electrode and the source and drain of each MOSFET by applying a first heat-treatment to the wafer so as to allow Co and Si to react with each other; and
(d) a step of removing the unreacted portions of the Co film and then applying a second heat-treatment to the wafer so as to reduce the resistance of the Co silicide layer.
When the CoSi2 layer is formed on the silicon surface by the reaction of Co with Si, the fabrication method of the semiconductor integrated circuit device according to the present invention reduces the sheet resistance of the CoSi2 layer to 10 xcexa9/square or below by using the high impurity Co target capable of providing the CoSi layer that has low temperature dependence on at least the first heat-treatment temperature and has improved film thickness controllability.
The high purity Co target used in the present invention has a Co purity of at least 99.99% and a Fe or Ni content of not greater than 10 ppm, or the sum of the Fe and Ni contents of not greater than 50 ppm. Preferably, the Co purity is at least 99.99% and the Fe and Ni contents are not greater than 10 ppm and more preferably, the Co purity is 99.999%.
The term xe2x80x9cwaferxe2x80x9d as used in this specification means a sheet-like article at least a part of which comprises a single, or a plurality of, single crystal regions (mainly silicon in the invention) after at least prescribed process steps that form the semiconductor integrated circuit device mainly on the main surface region thereof. The term xe2x80x9csemiconductor integrated circuit devicexe2x80x9d as used herein means not only those which are formed on ordinary single crystal wafers but on other substrates, such as TFT liquid crystals.
A summary of various aspects of the invention disclosed herein can be itemized as follows.
(1) A method of fabricating a semiconductor integrated circuit device comprising the steps of:
(a) forming MOSFETs on a main plane of a wafer;
(b) depositing a Co film in regions of the main plane of the wafer including at least the gate electrode and the source and drain of each MOSFET by sputtering using a high purity Co target;
(c) a step of applying a first heat-treatment to the wafer so as to allow Co and Si to react with each other and to form a Co silicide layer on the surfaces of the gate electrode and the source and drain of each MOSFET; and
(d) removing the unreacted portions of the Co film and applying a second heat-treatment to the wafer so as to reduce the resistance of the Co silicide layer.
(2) According to the method of fabricating a semiconductor integrated circuit device of the invention as described above, the Co purity of the Co target is at least 99.99% and the Fe or Ni content is not greater than 10 ppm.
(3) According to the method of fabricating a semiconductor integrated circuit device as described above, the Co purity of the Co target is at least 99.99% and the Fe and Ni contents are not greater than 50 ppm.
(4) According to the method of fabricating a semiconductor integrated circuit device as described above, the Co purity of the Co target is at least 99.99% and the Fe and Ni contents are not greater than 10 ppm.
(5) According to the method of fabricating a semiconductor integrated circuit device as described above, the Co purity of the Co target is 99.999%.
(6) According to the method of fabricating a semiconductor integrated circuit device as described above, the temperature of the first heat-treatment is from 475 to 525xc2x0 C.
(7) According to the method of fabricating a semiconductor integrated circuit device as described above, the temperature of the second heat-treatment is from 650 to 800xc2x0 C.
(8) According to the method of fabricating a semiconductor integrated circuit device as described above, the film thickness of the Co film is from 18 to 60 nm.
(9) According to the method of fabricating a semiconductor integrated circuit device as described above, the sheet resistance of the Co silicide layer after the application of the second heat-treatment is not greater than 10 xcexa9/square.
(10) According to the method of fabricating a semiconductor integrated circuit device as described above, the junction depth of the source and the drain is not greater than 0.3 xcexcm.
(11) A method of fabricating a semiconductor integrated circuit device according to the present invention comprises the steps of:
(a) depositing a polycrystalline silicon film and a first insulating film on a main plane of a wafer having a gate insulating film formed thereon, and patterning the first insulating film and the polycrystalline silicon film to thereby form a first gate electrode pattern in a first region of the wafer and a second gate electrode pattern in a second region thereof;
(b) implanting an impurity ion of a first conductivity type into the first region of the wafer to form first conductivity type semiconductor regions having a low impurity concentration in the wafer on both sides of the first gate electrode pattern, and implanting an impurity ion of a second conductivity type into the second region of the wafer to form second conductivity type semiconductor regions in the wafer on both sides of the second gate electrode pattern;
(c) patterning the second insulating film deposited on the main plane of the wafer to form side wall spacers on side walls of the first and second gate electrodes, and removing the first insulating films of the first and second gate electrode patterns to expose the surface of the polycrystalline silicon film;
(d) implanting an impurity ion of the first conductivity type into the first region of the wafer to form a first gate electrode of the first conductivity type by the polycrystalline silicon film of the first gate electrode pattern and to form first conductivity type semiconductor regions having a high impurity concentration in the wafer on both sides of the first gate electrode, and implanting an impurity ion of the second conductivity type into the second region of the wafer to form a second gate electrode of the second conductivity type by the polycrystalline silicon film of the second gate electrode pattern, and to form second conductivity type semiconductor regions having a high impurity concentration in the wafer on both sides of the second gate electrode;
(e) depositing a Co film on the main plane of the wafer by sputtering using a high purity Co target;
(f) applying a first heat-treatment to the wafer to allow Co and Si to react with each other to thereby form a Co silicide layer on the surface of the first and second gate electrodes and the surface of the first and second conductivity type semiconductor regions having a high impurity concentration; and
(g) removing the unreacted portion of the Co film and then applying a second heat-treatment to the wafer to lower the resistance of the Co silicide layer.
(12) According to the method of fabricating a semiconductor integrated circuit device of the present invention as described above, an operating power source voltage of the MOSFET is not higher than 2 V.
(13) According to the method of fabricating a semiconductor integrated circuit device as described above, the Co purity of the Co target is at least 99.99% and the Fe or Ni content is not greater than 10 ppm.
(14) According to the method of fabricating a semiconductor integrated circuit device as described above, the Co purity of the Co target is at least 99.99% and the Fe and Ni contents are not greater than 50 ppm.
(15) According to the method of fabricating a semiconductor integrated circuit device as described above, the Co purity of the Co target is at least 99.99% and the Fe and Ni contents are not greater than 10 ppm.
(16) According to the method of fabricating a semiconductor integrated circuit device as described above, the Co purity of the Co target is 99.999%.
(17) A method of fabricating a semiconductor integrated circuit device according to the present invention comprising the steps of:
(a) forming MOSFETs on a main plane of a wafer and then exposing the surface of the gate electrode and the source and drain of each MOSFET;
(b) depositing a Co film on the main plane of the wafer including the surface of the gate electrode and the source and drain of the MOSFET by sputtering using a high purity Co target;
(c) applying a first heat-treatment to the wafer to allow Co and Si to react with each other to thereby form a Co silicide layer made mainly of Co mono-silicide on the surface of the gate electrode, the source and the drain of the MOSFET;
(d) removing the unreacted portions of the Co film and then applying a second heat-treatment to cause phase transition of the Co silicide layer to a Co di-silicide layer made mainly of a Co di-silicide; and
(e) depositing a silicon oxide film containing an impurity doped thereto to the upper part of the MOSFET so as to getter a metal impurity, and then applying a third heat-treatment to the silicon oxide film.
(18) According to the method of fabricating a semiconductor integrated circuit device of the invention described above, the silicon oxide film containing the impurity doped thereto is a PSG film.
(19) According to the method of fabricating a semiconductor integrated circuit device as described above, the temperature of the third heat-treatment is from 700 to 800xc2x0 C.
It is an object of the present invention to provide a Salicide process capable of forming a Co silicide layer having a low resistance and a small junction leakage current.